Generally, phase detectors for use in phase locked loops (PLL's) are known in the art. In a PLL, a phase detector compares the phase of the reference signal to the phase of a divided voltage controlled oscillator (VCO) signal. The output of the phase detector then drives a charge pump which in turn drives a loop filter followed by a VCO. The VCO produces the VCO signal which is divided by a loop divider to generate the divided VCO signal.
Three common types of phase detectors known in the art include an exclusive-OR phase detector, a tri-state phase detector and a dual state phase detector. FIGS. 6-8 describe an exclusive-OR phase detector in accordance with the prior art. FIGS. 9-13 describe a tri-state phase detector in accordance with the prior art. FIGS. 14-21 describe a dual state phase detector in accordance with the prior art.
Turning first to the exclusive-OR phase detector, FIG. 6 illustrates a block diagram of an exclusive-OR phase detector 600 in accordance with the prior art. FIG. 7 illustrates a timing diagram 700 for the exclusive-OR phase detector 600 of FIG. 6 in accordance with the prior art. FIG. 8 illustrates a graph 800 depicting output voltage versus phase for the exclusive-OR phase detector 600 of FIG. 6 in accordance with the prior art.
In FIG. 6, the exclusive-OR phase detector 600 has two input terminals and an output terminal. A first terminal receives a divided reference frequency signal 604 from a reference frequency divider (not shown). A second terminal receives a divided VCO frequency signal 606 from a loop divider (not shown). The output terminal produces a phase error signal 608. Typically, the phase error signal is a voltage signal.
The exclusive-OR phase detector 600 operates according to a timing diagram 700 of the waveforms represented in FIG. 7 and according to the following truth table.
Source 1 (604) Source 2 (606) Output (608) 0 0 0 0 1 1 1 0 1 1 1 0
When the two sources produce signals 604 and 606 that are in phase, the output voltage 608 is at a logic zero level. When the two sources produce signals 604 and 606 that are 180 degrees out of phase, then the output voltage 608 is at a logic high level (typically, a logic supply voltage represented by Vcc). Any condition of phase shift between the logic zero level and the logic high level results in the output voltage 608 being averaged between the logic zero level and the logic high level. The output voltage 608 of the exclusive-OR phase detector 600 is filtered by a filter (not shown) to reduce the large variation between the logic zero level and the logic high level.
A graph 800 of the average output voltage 608 versus phase error for the exclusive-OR phase detector 600 is shown in FIG. 8. In FIG. 8, a gain of the exclusive-OR phase detector 600 is represented as the slope of the average output voltage 608 (Vcc) versus phase. In FIG. 8, the slope is Vcc/phase volts per radian.
The exclusive-OR phase detector 600 has at least two disadvantages. First, the same output voltage is generated for positive and negative phase errors. Thus, to lock the PLL at zero phase error the exclusive-OR phase detector 600 needs to be modified. Second, output voltage 608 of the exclusive-OR phase detector 600 depends on the pulse width of the input pulses from the two input signals 604 and 606. Thus, if one signal has narrow pulses and the other signal has wide pulses then the gain of the exclusive-OR phase detector 600 will be dramatically different.
Turning next to the tri-state phase detector, FIG. 9 illustrates a block diagram of a tri-state phase detector 901 and a charge pump 903 in accordance with the prior art. The tri-state phase detector 901 is generally an improvement over the exclusive-OR phase detector 600.
In FIG. 9, the tri-state phase detector 901 generally includes a first D-type flip flop 902, a second D-type flip flop 904, and an AND gate 906. The first D-type flip flop 902 has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to a positive supply voltage 908. The second terminal is coupled to receive a divided reference frequency signal 910 (Fref). The third terminal generates a first output signal 912. The fourth terminal generates a second output signal 914 (i.e., the UP (up) signal). The fifth terminal is coupled to receive a reset signal 924. The second D-type flip flop 904 has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to the positive supply voltage 916. The second terminal is coupled to receive a divided VCO frequency signal 918 (Fvco). The third terminal generates a first output signal 920. The fourth terminal generates a second output signal 922 (i.e., the DN (down) signal). The fifth terminal is coupled to receive the reset signal 924.
In FIG. 9, the charge pump 903 generally includes a first current source 926 and a second current source 928. The first current source 926 has a first terminal, a second terminal and a third terminal. The first terminal is coupled to the positive supply voltage 932. The second terminal is coupled to receive the UP signal 914 from the first D-type flip flop 902. The third terminal generates an output current signal 930. The second current source 928 has a first terminal, a second terminal and a third terminal. The first terminal 932 is coupled to the third terminal of the first current source 926 and is operative to produce the output current signal 930. The second terminal is coupled to receive the DN signal 922 from the second D-type flip flop 904. The third terminal is coupled to a ground potential.
Generally, in operation of the tri-state phase detector 901, a phase difference between Fref 910 and Fvco cause the UP signal 914 and the DN signal 922 of the tri-state phase detector 901 to vary. The UP signal 914 and the DN signal 922 of the tri-state phase detector 901 drive the two current sources 926 and 928 of the charge pump 903 which charge or discharge loop filter capacitors (not shown in FIG. 9) to form a voltage control for a VCO (not shown in FIG. 9) in a PLL (not shown in FIG. 9).
Particularly, in operation of the tri-state phase detector 901, consider the case where Fref 910 rises before Fvco 918, wherein both of the D-type flip flops 902 and 904 are edge triggered. On the rising edge of Fref 910, the first D-type flip flop 902 sets its first output signal 912 to a logic high and its second output signal 914 to a logic low. Both output signals 912 and 914 will remain in this state until Fvco 918 rises. When Fvco 918 rises then the second D-type flip flop 904 sets its first output signal 920 a logic high and its second output signal 922 to a logic low. The logic high of the first output signal 912 from the first D-type flip flop 902 and the logic high of the first output signal 920 from the second D-type flip flop 904 cause the AND gate 906 to generate the reset signal 924 at a logic high to reset both flip flops 902 and 904. When this reset occurs the tri-state phase detector 901 returns to its initial state and is ready to receive another set of pulses from Fref 910 and Fvco 918. This operation of the tri-state phase detector 901 causes the UP signal 914 will be low for a time which is equal to the delay between Fref 910 and Fvco 918. The logic low pulse from the UP signal 914 drives the first current source 926 which charges the loop filter capacitors in the PLL to a higher voltage. Responsive to the higher voltage, the VCO in the PLL increases its frequency to cause a pulse of Fvco 918 to occur sooner at a next sampling instance which in turn reduces the pulse width produced at the UP signal 914. This operation will continue until Fvco 918 occurs at the same time as Fref 910 resulting in essentially no pulse being produced at the UP signal 914. Alternatively, if the Fvco 918 had risen before Fref 910 then the DN signal 922 would have acted in an analogous manner, as described with the UP signal 914, to reduce a pulse of Fvco 918.
FIG. 10 illustrates a timing diagram 1000 for the tri-state phase detector 901 of FIG. 9 in accordance with the prior art. The timing diagram 1000 shows typical outputs for various exemplary phase differences. If Fref 910 leads Fvco 918 by an amount approaching 360 degrees, then the UP signal pulse 914 will be active for almost all time. This results in a positive current signal 930 being generated for the loop filter in the PLL. If Fvco 918 leads by an amount approaching 360 degrees, then the DN signal pulse 922 will be active for almost all time. This results in a negative current signal 930 being generated for the loop filter in the PLL.
FIG. 11 illustrates a graph 1100 of an output current versus phase offset for the tri-state phase detector 901 and the charge pump 903 of FIG. 9 when an up current source 926 and a down current source 928 are balanced in accordance with the prior art. In this graph 1100 the phase detector gain is Io/2p amps/radian. In comparison to the exclusive-OR phase detector 600, the problem of locking at zero phase offset has been solved. This can be seen in that the characteristic is an odd function about the graph's origin (i.e., the sign of the phase error is taken into account). For offsets beyond +/-2p, the gain will vary depending on the exact frequency relationship, but the net output current will always be such that the PLL will pull in the signal. This is known as frequency acquisition. By modifying the tri-state phase detector 901, it is possible to cause the net output current to hold at the desired up or down state (thus, resulting in the fastest possible tuning), if two or more pulses of one input 910 or 918 occur for each pulse of the other input 910 or 918.
Note that in the timing diagram 1000 showing representative pulses, the UP signal 914 and the DN signal 922 have pulses with minimum widths at the end of the control pulse, no matter what the net pulse is to be, due to the finite delay associated with the AND gate 906 and the flip flop reset. This minimum pulse is unavoidable in any real circuit and causes reference spurs. The reference spurs are caused by the minimum width pulse trains modulating the VCO in the PLL at the reference frequency which generate the spurs at harmonic frequencies of the reference frequency. In an ideal tri-state phase detector 901 with no minimum pulse width the correction term would tend to zero and thus eliminating any reference spurs. Ideally, even with the minimum pulses there would be no reference spurs, since both sources turn on to provide signals 910 and 918 which cancel each other. However, in reality the pulses are not perfectly time and amplitude balanced and thus spurs are produced. To overcome this problem, a delay is typically added at the output of the AND gate 906 to establish a minimum pulse width which is typically 4 to 10 nsec. This is done because in reality current sources do not turn on instantaneously.
FIG. 12 illustrates a timing diagram 1200 for the tri-state phase detector 901 and the charge pump 903 of FIG. 9 in accordance with the prior art. The timing diagram 1200 shows the operation of the pair of current sources 1026 and 1028 resulting in a net up pulse with and without minimum pulse width. If the minimum pulse width is not enough to insure that the current sources turn on, then there will be a range of small phase offsets for which the PLL will not respond. This is known as a dead zone. If a dead zone occurs, then once the PLL is within the dead zone the VCO is free running. Due to leakage currents the control voltage to the VCO will drop until the PLL moves out of the dead zone, at which time the PLL will correct the voltage to the other side of the zone and the process will repeat. The net result is a "sawtooth like" modulation of the VCO at a very low rate. Therefore, even though the tri-state phase detector 901 has improved in noise performance over the exclusive-OR phase detector 600, the need for filtering of reference spurs is still required due to the minimum pulse output and leakage currents on the loop filter.
The tri-state phase detector 901 also suffers from another non-ideally which limits its usefulness in applications which require high linearity. If the UP current signal 914 and the DN current signal 922 are not precisely balanced then the gain of the tri-state phase detector 901 will differ depending on the sign of the phase error. FIG. 13 shows an example of this situation. FIG. 13 illustrates a graph 1300 of an output current versus phase offset for the tri-state phase detector 901 and the charge pump 903 of FIG. 9 when the up current source 926 and the down current source 928 are not balanced in accordance with the prior art. In FIG. 13, the slope of plot 1302 is different than that of plot 1304. Although this not an issue for a standard synthesizer, in a fractional N synthesizer this imbalance will introduce non-linearities which will result in spurious outputs.
Turning next to the dual state phase detector, FIG. 14 illustrates a block diagram of a dual state phase detector 1401 and a charge pump 1403 in accordance with the prior art. To overcome the linearity issue associated with the tri-state phase detector 901, frequency synthesizers may employ a dual state phase detector 1401, as shown in FIG. 14.
In FIG. 14, the dual state phase detector 1401 generally includes a first D-type flip flop 1402 and a second D-type flip flop 1404. The first D-type flip flop 1402 has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to a positive supply voltage 1406. The second terminal is coupled to receive a divided reference frequency signal 1422 (Fref). The third terminal generates a first output signal 1410. The fourth terminal is not used. The fifth terminal is coupled to receive a reset signal 1412. The second D-type flip flop 1404 has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to the positive supply voltage 1408. The second terminal is coupled to receive a divided VCO frequency signal 1424 (Fvco). The third terminal generates a first output signal 1414 (i.e., the DN (down) signal). The fourth terminal is not used. The fifth terminal is coupled to receive the reset signal 1412.
In FIG. 14, the charge pump 1403 generally includes a first current source 1416 and a second current source 1418. The first current source 1416 has a first terminal and a second terminal. The first terminal is coupled to a positive supply voltage. The third terminal generates an output current signal 1420. The second current source 1418 has a first terminal, a second terminal and a third terminal. The first terminal is coupled to the second terminal of the first current source 1416 and is operative to produce the output current signal 1420. The second terminal is coupled to the third terminal of the second D-type flip flop 904 and is coupled to receive the DN signal 1414. The third terminal is coupled to a ground potential.
FIG. 15 illustrates a timing diagram 1500 for the dual state phase detector 1401 and the charge pump 1403 of FIG. 14 in a phased locked condition in accordance with the prior art. In the dual state phase detector 1401, the locked condition corresponds to a "square wave" of current of amplitude equal to I. This means that there are equal up and down current pulses and thus net zero charge transfer to the loop filter in the PLL. Note that in the dual state phase detector the condition of lock occurs when the input waveforms 1422 and 1424 are 180 degrees out of phase. If the phase of Fvco 1424 leads that of Fref 1422, then the duty cycle of the DN signal 1414 increases until the current is sinking I to ground continuously at 360 degrees. Alternatively, as the phase of Fvco 1424 approaches that of Fref 1422, the output current signal 1420 duty cycle will approach zero and the net result will be a continuous current sourced to the loop filter. By example, FIG. 16 illustrates a timing diagram for the dual state phase detector 1401 and the charge pump 1403 of FIG. 14 when Fvco 1424 leads Fref 1422 in accordance with the prior art.
FIG. 17 illustrates a graph 1700 of a net output current versus phase offset for the dual state phase detector 1403 of FIG. 14 when the up current source 1416 and the down current source 1418 are balanced 1702 and not balanced 1704 in accordance with the prior art. The dual state phase detector 1401 is nearly perfectly linear because the pulse width of the down current source 1418 is made to be twice the current, 2I, of the up current source 1416 while the up current source 1416 is made to be a constant current, I. Therefore, if an imbalance exists between the up 1416 and down 1418 current sources due to a decrease in the current provided by the up current source 1416, the balanced plot 1702 shifts along the y-axis to the unbalanced plot 1704 shown in dashed line, but the linearity of the unbalanced plot 1704 will not be affected.
FIG. 18 illustrates a timing diagram 1800 for the dual state phase detector 1401 and the charge pump 1403 of FIG. 14 when Fvco 1424 leads Fref 1422 and has a higher frequency than the Fref 1422 in accordance with the prior art. In FIG. 18, Fvco is at a second harmonic frequency of Fref. Note that the output current 1420 is almost equal to the locked condition of a square wave or zero net charge transfer out of the charge pump. If the phase error was zero, then this would be true. This situation occurs when Fref * A=Fvco*(A+1) where A is an integer. Most of the resulting waveforms of lout will not be square waves in these cases. However the net charge transfer will be zero. Therefore, the classical dual state phase detector has points of net zero output charge transfer at frequencies were A*Fref=(A+1) * Fvco if the phase of the input waveforms are correct. This can cause the PLL to falsely lock at integer ratios (other than 1:1) of the two input waveforms. Some of these integer ratios may be very close to the desired frequency and thus this type of phase detector may malfunction even for synthesizers with narrow tuning ranges. FIG. 18 shows a slight phase offset of the harmonic waveform. This is to point out that if the phase relationship of the second harmonic Fvco was not precisely aligned with Fref, then the phase detector output would have the correct polarity to steer the frequency correctly. Therefore, in the ideal situation the false lock to integer ratios other than 1:1 are metastable states since any movement in phase from the precise alignment will cause the loop to move away from the point. This is shown in FIG. 19 for two different integer ratios of frequencies. In this case the two false lock frequencies have characteristics which do not "cross the zero axis" of net current.
FIG. 19 illustrates a graph 1900 depicting a net output current versus phase for the phase detector 1401 and the charge pump 1403 of FIG. 14 operating without frequency steering in accordance with the prior art. Graphs of this type, as disclosed herein, are for general explanation purposes only and are not meant to represent a precise plot. The reason is that the phase error between two different frequencies would not be clearly defined. The purpose of this graph 1900 is to show that there will be multiple lock points above and below the desired point and that these points touch but do not cross the x-axis.
If the up 1416 and down 1418 current sources are precisely balanced in a 1 to 2 ratio, respectively, then plot of lout versus phase will be represented as shown in FIG. 19. However, if there is a slight imbalance in the currents of the up 1416 and down 1418 current sources, then a false lock will be possible. This false lock condition is shown in FIGS. 20 and 21. FIG. 20 illustrates a graph 2000 depicting a net output current versus phase for the phase detector 1401 and the charge pump 1403 of FIG. 14 operating with frequency steering produced by an increase in the up current source 1416 in accordance with the prior art. FIG. 21 illustrates a graph 2100 depicting a net output current versus phase for the phase detector 1401 and the charge pump 1403 of FIG. 14 operating with frequency steering produced by a decrease in the up current source 1416 in accordance with the prior art. In these cases an increase in the current provided by the up current source 1416 will cause false lock conditions on the positive x-axis and a decrease in the current provided by the up current source 1416 will cause false lock conditions on the negative x-axis. Either condition will cause incorrect phase detector operation.
Accordingly, there is a need for a phase detector for a phase locked loop that minimizes false locks between the phase of the divided reference frequency signal (Fref) 1422 and the phase of the divided voltage controlled oscillator frequency signal (Fvco) 1424.